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CY7C1304DV25
9-Mbit Burst of 4 Pipelined SRAM with QDRTM Architecture
Features
* Separate independent Read and Write data ports -- Supports concurrent transactions * 167-MHz Clock for high bandwidth -- 2.5 ns Clock-to-Valid access time * 4-Word Burst for reducing the address bus frequency * Double Data Rate (DDR) interfaces on both Read and Write Ports (data transferred at 333 MHz) @167 MHz * Two input clocks (K and K) for precise DDR timing -- SRAM uses rising edges only * Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches. * Single multiplexed address input bus latches address inputs for both Read and Write ports * Separate Port Selects for depth expansion * Synchronous internally self-timed writes * 2.5V core power supply with HSTL Inputs and Outputs * Available in 165-ball FBGA package (13 x 15 x 1.4 mm) * Variable drive HSTL output buffers * Expanded HSTL output voltage (1.4V-1.9V) * JTAG 1149.1 compatible test access port
Functional Description
The CY7C1304DV25 is a 2.5V Synchronous Pipelined SRAM equipped with QDRTM architecture. QDR architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write port has dedicated Data Inputs to support Write operations. QDR architecture has separate data inputs and data outputs to completely eliminate the need to "turn-around" the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. Addresses for Read and Write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the device's Read and Write ports are completely independent of one another. In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate (DDR) interfaces. Each address location is associated with four 18-bit words. Since data can be transferred into and out of the device on every rising edge of both input clock (K/K and C/C) memory bandwidth is maximized while simplifying system design by eliminating bus "turn-arounds." Depth expansion is accomplished with Port Selects for each port. Port selects allow each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.
Configurations
CY7C1304DV25 - 512K x 18
Logic Block Diagram (CY7C1304DV25)
D[17:0] 18
Write Write Reg Reg Write Reg Write Reg
A(16:0)
Write Add. Decode
Read Add. Decode
Address Register 17
128Kx18 Array
128Kx18 Array
128Kx18 Array
128Kx18 Array
Address Register
17
A(16:0)
K K
CLK Gen.
Control Logic
RPS C C
Read Data Reg. 72 Control Logic 36 Reg. 36 Reg. 18 Reg.
Vref WPS BWS[0:1]
18 Q[17:0]
Cypress Semiconductor Corporation Document #: 38-05628 Rev. *A
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised March 23, 2006
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CY7C1304DV25
Selection Guide
CY7C1304DV25-167 Maximum Operating Frequency Maximum Operating Current 167 400 Unit MHz mA
Pin Configuration 165-ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1304DV25 (512K x 18)
1 A B C D E F G H J K L M N P R NC NC NC NC NC NC NC NC NC NC NC NC NC NC TDO 2 Gnd/144M Q9 NC D11 NC Q12 D13 VREF NC NC Q15 NC D17 NC TCK 3 NC/36M D9 D10 Q10 Q11 D12 Q13 VDDQ D14 Q14 D15 D16 Q16 Q17 A 4 WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 BWS1 NC A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C 7 NC BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 NC Q7 NC D6 NC NC VREF Q4 D3 NC Q1 NC D0 TMS 11 NC Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI NC/18M Gnd/72M
Pin Definitions
Name D[17:0] WPS I/O InputSynchronous InputSynchronous InputSynchronous Description Data input signals, sampled on the rising edge of K and K clocks during valid Write operations. Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted active, a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port will cause D[17:0] to be ignored. Byte Write Select 0 and 1, active LOW. Sampled on the rising edge of the K and K clocks during Write operations. Used to select which byte is written into the device during the current portion of the Write operations. Bytes not written remain unaltered. BWS0 controls D[8:0] and BWS1 controls D[17:9]. All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written into the device. Address Inputs. Sampled on the rising edge of the K clock during active Read and Write operations. These address inputs are multiplexed for both Read and Write operations. Internally, the device is organized as 512Kb x 18 (4 arrays each of 128Kb x 18). Therefore, only 17 address inputs are needed to access the entire memory array. These inputs are ignored when the appropriate port is deselected. Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge of both the C and C clocks during Read operations or K and K when in single clock mode. When the Read port is deselected, Q[17:0] are automatically three-stated.
BWS0, BWS1
A
InputSynchronous
Q[17:0]
OutputsSynchronous
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CY7C1304DV25
Pin Definitions (continued)
Name RPS I/O InputSynchronous Description Read Port Select, active LOW. Sampled on the rising edge of positive input clock (K). When active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When deselected, the pending access is allowed to complete and the output drivers are automatically three-stated following the next rising edge of the C clock. Each read access consists of a burst of four sequential 18-bit transfers. Positive Input Clock for Output Data. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. Negative Input Clock for Output Data. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[17:0] when in single clock mode. All accesses are initiated on the rising edge of K. Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data through Q[17:0] when in single clock mode. Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. Q[17:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly to VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. TDO for JTAG. TCK pin for JTAG. TDI pin for JTAG. TMS pin for JTAG. Address expansion for 18M. This is not connected to the die and so can be connected to any voltage level. Address expansion for 36M. This is not connected to the die and so can be connected to any voltage level. Address expansion for 72M. This must be tied LOW on the CY7C1304DV25. Address expansion for 144M. This must be tied LOW on the CY7C1304DV25. Reference Voltage Input. Static input used to set the reference level for HSTL inputs and outputs as well as AC measurement points. Power supply inputs to the core of the device. Ground for the device. Power supply inputs for the outputs of the device. Not connected to the die. Can be tied to any voltage level. contention, thereby simplifying system design. Each access consists of four 18-bit data transfers in two clock cycles. Accesses for both ports are initiated on the rising edge of the positive input clock (K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K) and all output timing is referenced to the rising edge of output clocks (C and C, or K and K when in single clock mode). All synchronous data inputs (D[17:0]) pass through input registers controlled by the rising edge of input clocks (K and K). All synchronous data outputs (Q[17:0]) pass through output registers controlled by the rising edge of the output clocks (C and C, or K and K when in single clock mode).
C
InputClock
C
InputClock
K
InputClock InputClock Input
K ZQ
TDO TCK TDI TMS NC/18M NC/36M GND/72M GND/144M VREF VDD VSS VDDQ NC
Output Input Input Input N/A N/A Input Input InputReference Power Supply Ground Power Supply N/A
Introduction
Functional Overview The CY7C1304DV25 is a synchronous pipelined Burst SRAM equipped with both a Read port and a Write port. The Read port is dedicated to Read operations and the Write port is dedicated to Write operations. Data flows into the SRAM through the Write port and out through the Read port. These devices multiplex the address inputs in order to minimize the number of address pins required. By having separate Read and Write ports, the device completely eliminates the need to "turn-around" the data bus and avoids any possible data
Document #: 38-05628 Rev. *A
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CY7C1304DV25
All synchronous control (RPS, WPS, BWS[0:1]) inputs pass through input registers controlled by the rising edge of input clocks (K and K). Read Operations The CY7C1304DV25 is organized internally as 4 arrays of 128K x 18. Accesses are completed in a burst of four sequential 18-bit data words. Read operations are initiated by asserting RPS active at the rising edge of the positive input clock (K). The address presented to Address inputs are stored in the Read address register. Following the next K clock rise the corresponding lowest order 18-bit word of data is driven onto the Q[17:0] using C as the output timing reference. On the subsequent rising edge of C the next 18-bit data word is driven onto the Q[17:0]. This process continues until all four 18-bit data words have been driven out onto Q[17:0]. The requested data will be valid 2.5 ns from the rising edge of the output clock (C and C, or K and K when in single clock mode, 167-MHz device). In order to maintain the internal logic, each Read access must be allowed to complete. Each Read access consists of four 18-bit data words and takes 2 clock cycles to complete. Therefore, Read accesses to the device can not be initiated on two consecutive K clock rises. The internal logic of the device will ignore the second Read request. Read accesses can be initiated on every other K clock rise. Doing so will pipeline the data flow such that data is transferred out of the device on every rising edge of the output clocks (C and C, or K and K when in single clock mode). When the read port is deselected, the CY7C1304DV25 will first complete the pending read transactions. Synchronous internal circuitry will automatically three-state the outputs following the next rising edge of the positive output clock (C). This will allow for a seamless transition between devices without the insertion of wait states in a depth expanded memory. Write Operations Write operations are initiated by asserting WPS active at the rising edge of the positive input clock (K). On the following K clock rise the data presented to D[17:0] is latched and stored into the lower 18-bit Write Data register provided BWS[1:0] are both asserted active. On the subsequent rising edge of the negative input clock (K) the information presented to D[17:0] is also stored into the Write Data Register provided BWS[1:0] are both asserted active. This process continues for one more cycle until four 18-bit words (a total of 72 bits) of data are stored in the SRAM. The 72 bits of data are then written into the memory array at the specified location. Therefore, Write accesses to the device can not be initiated on two consecutive K clock rises. The internal logic of the device will ignore the second Write request. Write accesses can be initiated on every other rising edge of the positive clock (K). Doing so will pipeline the data flow such that 18-bits of data can be transferred into the device on every rising edge of the input clocks (K and K). When deselected, the write port will ignore all inputs after the pending Write operations have been completed. Byte Write Operations Byte Write operations are supported by the CY7C1304DV25. A Write operation is initiated as described in the Write Operation section above. The bytes that are written are determined by BWS0 and BWS1 which are sampled with each set Document #: 38-05628 Rev. *A of 18-bit data word. Asserting the appropriate Byte Write Select input during the data portion of a write will allow the data being presented to be latched and written into the device. De-asserting the Byte Write Select input during the data portion of a write will allow the data stored in the device for that byte to remain unaltered. This feature can be used to simplify Read/Modify/Write operations to a Byte Write operation. Single Clock Mode The CY7C1304DV25 can be used with a single clock that controls both the input and output registers. In this mode the device will recognize only a single pair of input clocks (K and K) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K and C/C clocks. All timing parameters remain the same in this mode. To use this mode of operation, the user must tie C and C HIGH at power-on. This function is a strap option and not alterable during device operation. Concurrent Transactions The Read and Write ports on the CY7C1304DV25 operate completely independently of one another. Since each port latches the address inputs on different clock edges, the user can Read or Write to any location, regardless of the transaction on the other port. If the ports access the same location at the same time, the SRAM will deliver the most recent information associated with the specified address location. This includes forwarding data from a Write cycle that was initiated on the previous K clock rise. Read accesses and Write access must be scheduled such that one transaction is initiated on any clock cycle. If both ports are selected on the same K clock rise, the arbitration depends on the previous state of the SRAM. If both ports were deselected, the Read port will take priority. If a Read was initiated on the previous cycle, the Write port will assume priority (since Read operations can not be initiated on consecutive cycles). If a Write was initiated on the previous cycle, the Read port will assume priority (since Write operations can not be initiated on consecutive cycles). Therefore, asserting both port selects active from a deselected state will result in alternating Read/Write operations being initiated, with the first access being a Read. Depth Expansion The CY7C1304DV25 has a Port Select input for each port. This allows for easy depth expansion. Both Port Selects are sampled on the rising edge of the positive input clock only (K). Each port select input can deselect the specified port. Deselecting a port will not affect the other port. All pending transactions (Read and Write) will be completed prior to the device being deselected. Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM, The allowable range of RQ to guarantee impedance matching with a tolerance of 15% is between 175 and 350, with VDDQ = 1.5V. The output impedance is adjusted every 1024 cycles upon power-up to account for drifts in supply voltage and temperature.
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CY7C1304DV25
Application Example[1]
Truth Table[2,3,4,5,6,7]
Operation Write Cycle: L-H Load address on the rising edge of K; wait one cycle; input write data on two consecutive K and K rising edges. Read Cycle: L-H Load address on the rising edge of K; wait one cycle; read data on two consecutive C and C rising edges. NOP: No operation Standby: Clock stopped L-H Stopped K RPS H[8] WPS L[9] DQ D(A+00)at K(t+1) DQ D(A+01) at K(t+1) DQ D(A+10) at K(t+2) DQ D(A+11) at K(t+2)
L[9]
X
Q(A+00) at C(t+1)
Q(A+01) at C(t+1)
Q(A+10) at C(t+2)
Q(A+11) at C(t+2)
H X
H X
D=X Q = High-Z Previous state
D=X Q = High-Z
D=X Q = High-Z
D=X Q = High-Z
Previous state Previous state Previous state
Write Cycle Descriptions[2,10]
BWS0 L L L L H H H H BWS1 L L H H L L H H K L-H L-H L-H L-H K L-H L-H L-H L-H Comments During the Data portion of a Write sequence, both bytes (D[17:0]) are written into the device. During the Data portion of a Write sequence, both bytes (D[17:0]) are written into the device. During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered. During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered. During the Data portion of a Write sequence, only the upper byte (D[17:9]) is written into the device. D[8:0] will remain unaltered. During the Data portion of a Write sequence, only the upper byte (D[17:9]) is written into the device. D[8:0] will remain unaltered. No data is written into the device during this portion of a Write operation. No data is written into the device during this portion of a Write operation.
Notes: 1. The above application shows four QDR-I being used. 2. X = Don't Care, H = Logic HIGH, L = Logic LOW, represents rising edge. 3. Device will power-up deselected and the outputs in a three-state condition. 4. "A" represents address location latched by the devices when transaction was initiated. A+00, A+01, A+10 and A+11 represents the address sequence in the burst. 5. "t" represents the cycle at which a Read/Write operation is started. t+1 and t+2 are the first and second clock cycles respectively succeeding the "t" clock cycle. 6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode. 7. It is recommended that K = K and C = C when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 8. If this signal was LOW to initiate the previous cycle, this signal becomes a don't care for this operation. 9. This signal was HIGH on previous K clock rise. Initiating consecutive Read or Write operations on consecutive K clock rises is not permitted. The device will ignore the second Read request. 10. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS0 and BWS1 can be altered on different portions of a write cycle, as long as the set-up and hold requirements are achieved.
Document #: 38-05628 Rev. *A
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IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan test access port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-1900. The TAP operates using JEDEC standard 2.5V I/O logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. Test Access Port--Test Clock The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register. Test Data-Out (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (see Instruction codes). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. Performing a TAP Reset A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a high-Z state. TAP Registers Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the Document #: 38-05628 Rev. *A TDI and TDO pins as shown in TAP Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture IR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all of the input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and Output ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction Page 6 of 18
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is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High-Z state until the next command is given during the "Update IR" state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required--that is, while data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. EXTEST The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift-DR controller state. EXTEST Output Bus Tri-state IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode. The boundary scan register has a special bit located at bit #47. When this scan cell, called the "extest output bus tri-state", is latched into the preload register during the "Update-DR" state in the TAP controller, it will directly control the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output bus into a High-Z condition. This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the "Shift-DR" state. During "Update-DR", the value loaded into that shift-register cell will latch into the preload register. When the EXTEST instruction is entered, this bit will directly control the output Q-bus pins. Note that this bit is pre-set HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the "Test-Logic-Reset" state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions.
Document #: 38-05628 Rev. *A
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TAP Controller State Diagram[11] 1 TEST-LOGIC RESET 0 0 TEST-LOGIC/ IDLE 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1
Note: 11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
1
1 SELECT IR-SCAN 0 1 CAPTURE-IR 0
0
SHIFT-IR 1
0
1
EXIT1-IR 0
1
0
PAUSE-IR 1 0 EXIT2-IR 1 UPDATE-IR 1 0
0
0
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TAP Controller Block Diagram
0 Bypass Register TDI Selection Circuitry 31 30 29 . . 2 Instruction Register 2 1 0 1 0 Selection Circuitry TDO
Identification Register 106 . . . . 2 1 0
Boundary Scan Register
TCK TMS
TAP Controller
TAP Electrical Characteristics Over the Operating Range[12, 15, 17]
Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input and Output Load Current GND VI VDDQ Test Conditions IOH = -2.0 mA IOH = -100 A IOL = 2.0 mA IOL = 100 A 1.7 -0.3 -5 Min. 1.7 2.1 0.7 0.2 VDD+0.3 0.7 5 Max. Unit V V V V V V A
TAP AC Switching Characteristics Over the Operating Range [13, 14]
Parameter tTCYC tTF tTH tTL Set-up Times tTMSS tTDIS tCS Hold Times tTMSH tTDIH tCH TMS Hold after TCK Clock Rise TDI Hold after Clock Rise Capture Hold after Clock Rise 10 10 10 ns ns ns TMS Set-up to TCK Clock Rise TDI Set-up to TCK clock Rise Capture Set-up to TCK Rise 10 10 10 ns ns ns TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH TCK Clock LOW 20 20 Description Min. 50 20 Max. Unit ns MHz ns ns
Notes: 12. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table. 13. Parameters tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 14. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
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TAP AC Switching Characteristics Over the Operating Range (continued)[13, 14]
Parameter Output Times tTDOV tTDOX TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid 0 20 ns ns Description Min. Max. Unit
TAP Timing and Test Conditions[14]
1.25V 2.5V 50 TDO Z0 = 50 CL = 20 pF 0V 1.25V ALL INPUT PULSES
(a)
GND
tTH
tTL
Test Clock TCK
tTMSS tTMSH
tTCYC
Test Mode Select TMS
tTDIS tTDIH
Test Data-In TDI
Test Data-Out TDO
tTDOX
tTDOV
Identification Register Definitions
Value Instruction Field Revision Number (31:29) Cypress Device ID (28:12) Cypress JEDEC ID (11:1) ID Register Presence (0) CY7C1304DV25 000 01011010011010110 00000110100 1 Version number. Defines the type of SRAM. Allows unique identification of SRAM vendor. Indicate the presence of an ID register. Description
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CY7C1304DV25
Scan Register Sizes
Register Name Instruction Bypass ID Boundary Scan Bit Size 3 1 32 107
Instruction Codes
Instruction EXTEST IDCODE SAMPLE Z RESERVED SAMPLE/PRELOAD RESERVED RESERVED BYPASS Code 000 001 010 011 100 101 110 111 Description Captures the Input/Output ring contents. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.
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CY7C1304DV25
Boundary Scan Order
Bit # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Bump ID 6R 6P 6N 7P 7N 7R 8R 8P 9R 11P 10P 10N 9P 10M 11N 9M 9N 11L 11M 9L 10L 11K 10K 9J 9K 10J 11J Bit # 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 Bump ID 11H 10G 9G 11F 11G 9F 10F 11E 10E 10D 9E 10C 11D 9C 9D 11B 11C 9B 10B 11A Internal 9A 8B 7C 6C 8A 7A Bit # 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Bump ID 7B 6B 6A 5B 5A 4A 5C 4B 3A 1H 1A 2B 3B 1C 1B 3D 3C 1D 2C 3E 2D 2E 1E 2F 3F 1G 1F Bit # 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 Bump ID 3G 2G 1J 2J 3K 3J 2K 1K 2L 3L 1M 1L 3N 3M 1N 2M 3P 2N 2P 1P 3R 4R 4P 5P 5N 5R
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CY7C1304DV25
Maximum Ratings
(Above which the useful life may be impaired.) Storage Temperature ................................ -65C to + 150C Ambient Temperature with Power Applied............................................ -55C to + 125C Supply Voltage on VDD Relative to GND....... -0.5V to + 3.6V Supply Voltage on VDDQ Relative to GND ..... -0.5V to + VDD DC Voltage Applied to Outputs in High Z State .................................... -0.5V to VDDQ + 0.5V DC Input Voltage[15] ...............................-0.5V to VDD + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-Up Current ................................................... > 200 mA
Operating Range
Range Com'l Ind'l Ambient Temperature (TA) 0C to +70C -40C to +85C VDD[16] 2.5 0.1V VDDQ[16] 1.4V to 1.9V
Electrical Characteristics Over the Operating Range [17]
DC Electrical Characteristics Over the Operating Range Parameter VDD VDDQ VOH VOL VOH(LOW) VOL(LOW) VIH VIL IX IOZ VREF IDD Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage[15] Input LOW Voltage[15, 20] GND VI VDDQ GND VI VDDQ, Output Disabled Typical value = 0.75V VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC Max. VDD, Both Ports Deselected, VIN VIH or VIN VIL' f = fMAX = 1/tCYC, Inputs Static Test Conditions Min. VREF + 0.2 - Typ. - - Input Load Current Output Leakage Current Input Reference Voltage[21] VDD Operating Supply Note 18 Note 19 IOH = -0.1 mA, Nominal Impedance IOL = 0.1 mA, Nominal Impedance Test Conditions Min. 2.4 1.4 VDDQ/2 - 0.12 VDDQ/2 - 0.12 VDDQ - 0.2 VSS VREF + 0.1 -0.3 -5 -5 0.68 0.75 Typ. 2.5 1.5 Max. 2.6 1.9 VDDQ/2 + 0.12 VDDQ/2 + 0.12 VDDQ 0.2 VDDQ + 0.3 VREF - 0.1 5 5 0.95 400 Unit V V V V V V V V A A V mA
ISB1
Automatic Power-Down Current Description Input HIGH Voltage Input LOW Voltage
200
mA
AC Input Requirements Over the Operating Range Parameter VIH VIL Max. - VREF -0.2 Unit V V
Notes: 15. Overshoot: VIH(AC) < VDDQ +0.85V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > -1.5V (Pulse width less than tCYC/2). 16. Power-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 17. All voltage referenced to Ground. 18. Output are impedance controlled. IOH = -(VDDQ/2)/(RQ/5) for values of 175 <= RQ <= 350. 19. Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 <= RQ <= 350. 20. This spec is for all inputs except C and C Clock. For C and C Clock, VIL(Max.) = VREF - 0.2V. 21. VREF (Min.) = 0.68V or 0.46VDDQ, whichever is larger, VREF (Max.) = 0.95V or 0.54VDDQ, whichever is smaller.
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CY7C1304DV25
Thermal Resistance[22]
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 165 FBGA Package 16.7 2.5 Unit C/W C/W
Capacitance[22]
Parameter CIN CCLK CO Description Input Capacitance Clock Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD = 2.5V. VDDQ = 1.5V Max. 5 6 7 Unit pF pF pF
AC Test Loads and Waveforms
VREF = 0.75V VREF OUTPUT Device Under Test Z0 = 50 RL = 50 VREF = 0.75V 0.75V VREF OUTPUT Device Under Test ZQ 5 pF 0.25V Slew Rate = 2 V/ns 0.75V R = 50 ALL INPUT PULSES 1.25V 0.75V
[23]
ZQ
RQ = 250
(a)
RQ = 250 (b)
Switching Characteristics Over the Operating Range [23]
Cypress Consortium Parameter Parameter tPower tCYC tKH tKL tKHKH tKHCH tSA tSC tSD
[24]
167 MHz Description VCC (typical) to the First Access Read or Write Min. 10 6.0 2.4 2.4 2.7 0.0 0.7 0.7 0.7 3.3 2.0 Max. Unit s ns ns ns ns ns ns ns ns
Cycle Time tKHKH tKHKL tKLKH tKHKH tKHCH tSA tSC tSD K Clock and C Clock Cycle Time Input Clock (K/K and C/C) HIGH Input Clock (K/K and C/C) LOW K/K Clock Rise to K/K Clock Rise and C/C to C/C Rise (rising edge to rising edge) K/K Clock Rise to C/C Clock Rise (rising edge to rising edge) Address Set-up to Clock (K and K) Rise Control Set-up to Clock (K and K) Rise (RPS, WPS, BWS0, BWS1) D[17:0] Set-up to Clock (K and K) Rise
Set-up Times
Notes: 22. Tested initially and after any design or process change that may affect these parameters. 23. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V,Vref = 0.75V, RQ = 250 Ohms, VDDQ = 1.5V, input pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC test loads. 24. This part has a voltage regulator that steps down the voltage internally; tPower is the time power needs to be supplied above VDD minimum initially before a Read or Write operation can be initiated.
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CY7C1304DV25
Switching Characteristics Over the Operating Range (continued)[23]
Cypress Consortium Parameter Parameter Hold Times tHA tHC tHD tCO tDOH tCHZ tCLZ tHA tHC tHD tCHQV tCHQX tCHZ tCLZ Address Hold after Clock (K and K) Rise Control Signals Hold after Clock (K and K) Rise (RPS, WPS, BWS0, BWS1) D[17:0] Hold after Clock (K and K) Rise C/C Clock Rise (or K/K in single clock mode) to Data Valid Data Output Hold after Output C/C Clock Rise (Active to Active) Clock (C and C) Rise to High-Z (Active to High-Z) Clock (C and C) Rise to Low-Z[25, 26]
[25, 26]
167 MHz Description Min. 0.7 0.7 0.7 2.5 1.2 2.5 1.2 Max. Unit ns ns ns ns ns ns ns
Output Times
Notes: 25. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 100 mV from steady-state voltage. 26. At any given voltage and temperature tCHZ is less than tCLZ and, tCHZ less than tCO.
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CY7C1304DV25
Switching Waveforms[27, 28, 29]
NOP 1
K tKH K t KL t CYC t KHKH
READ 2
WRITE 3
READ 4
WRITE 5
NOP 6
7
RPS t SC WPS A t SA A0 t HA t SD D D10 D11 A1 t HD t SD D12 D13 D30 D31 D32 D33 A2 A3 t HD t HC t SC t HC
Q Qx3 t KHCH t CO
Q00
Q01
Q02
Q03
Q20
Q21
Q22
Q23
t DOH t CLZ C tKHCH C tCYC tKHKH tKH tKL tCO t DOH tCHZ
DON'T CARE
UNDEFINED
Notes: 27. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1. 28. Outputs are disabled (High-Z) one clock cycle after a NOP 29. In this example, if address A2 = A1, then data Q20 = D10, Q21 = D11, Q22 = D12, and Q23 = D13. Write data is forwarded immediately as read results.This note applies to the whole diagram.
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CY7C1304DV25
Ordering Information
"Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered". Speed (MHz) 167 Ordering Code CY7C1304DV25-167BZC CY7C1304DV25-167BZXC CY7C1304DV25-167BZI CY7C1304DV25-167BZXI Package Diagram Package Type 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead free 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead free Industrial Operating Range Commercial
51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Package Diagram
165 FBGA 13 x 15 x 1.40 MM BB165D/BW165D 165-ball FBGA (13 x 15 x 1.4 mm) (51-85180)
BOTTOM VIEW TOP VIEW TOP VIEW PIN 1 CORNER PIN 1 CORNER
1 A B C D E F G 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7
PIN BOTTOM VIEW 1 CORNER PIN 1 CORNER O0.05 M C O0.25 MO0.05 M C CAB O0.25 O0.50 -0.06 (165X) M C A B
+0.14 4 6 5
O0.50 -0.06 (165X)
3 +0.14 2 1
1 A B
2
3
4
5
6
7
8
9
10
11
11
10
9
8
7
6
5
4
3
2
1A
B
A B C D E F G H J K L M N P R
D E F
1.00
C
1.00
C D E F G
15.000.10
15.000.10
15.000.10
H J K L M N P R
G H J K
14.00 15.000.10
H
14.00
J K
M N P R
7.00
L
7.00
L M N P R
A A
A A 5.00 5.00 10.00 10.00 B B 13.000.10 13.000.10 0.15(4X) B B 13.000.10
1.00 1.00
13.000.10
1.40 MAX.
0.530.05 0.25 C
0.15(4X)
SEATING PLANE 0.36 C 0.36 C SEATING PLANE 0.350.06
NOTES : NOTES : SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) PACKAGE WEIGHT : 0.475gNON-SOLDER MASK DEFINED (NSMD) SOLDER PAD TYPE : JEDEC REFERENCE : MO-216 / DESIGN 4.6C PACKAGE WEIGHT : 0.475g PACKAGE CODE : BB0AC : MO-216 / DESIGN 4.6C JEDEC REFERENCE PACKAGE CODE : BB0AC
51-85180-*A
0.25 C
1.40 MAX.
0.530.05
0.15 C
0.15 C
Quad Data RateTM SRAM and QDRTM SRAM comprise a new family of products developed by Cypress, IDT, NEC and Samsung. All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05628 Rev. *A
0.350.06
51-85180-*A
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(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1304DV25
Document History Page
Document Title: CY7C1304DV25 9-Mbit Burst of 4 Pipelined SRAM with QDRTM Architecture Document Number: 38-05628 REV. ** *A ECN NO. 253049 436864 Issue Date See ECN See ECN Orig. of Change SYT NXR New Data Sheet Converted from Preliminary to Final. Removed 133 MHz & 100 MHz from product offering. Included Industrial Operating Range. Changed C/C Description in the Features Section & Pin Description Table. Changed tTCYC from 100 ns to 50 ns, changed tTF from 10 MHz to 20 MHz and changed tTH and tTL from 40 ns to 20 ns in TAP AC Switching Characteristics table Modified the ZQ pin definition as follows: Alternately, this pin can be connected directly to VDDQ, which enables the minimum impedance mode Included Maximum Ratings for Supply Voltage on VDDQ Relative to GND Changed the Maximum Ratings for DC Input Voltage from VDDQ to VDD. Modified the Description of IX from Input Load current to Input Leakage Current on page # 13. Modified test condition in note# 16 from VDDQ < VDD to VDDQ VDD Updated the Ordering Information table and replaced the Package Name Column with Package Diagram. Description of Change
Document #: 38-05628 Rev. *A
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